Mahesh Iyer is an Intel Sr. Fellow and chief Electronic Design Automation (EDA) software and FPGA architect in the Programmable Solutions Group (PSG)/Datacenter and AI group. He is responsible for defining and carrying out the technical vision and direction for the Quartus compiler organization and its products with synergies in FPGA architecture design. Iyer’s technical leadership and innovations in overhauling Quartus algorithms and in co-designing with hardware architecture have played a significant role towards AgilexTM achieving fabric performance/watt leadership. Iyer mentors PSG’s university research programs and serves on Intel’s Corporate Research Council. Prior to Altera/Intel, Iyer served as the software architect and co-author for some of Synopsys' most successful EDA products, including Design Compiler, IC Compiler, and VCS. Iyer’s pioneering technical inventions and contributions in ASIC Electronic Design Automation (EDA) algorithms, flows, and methodologies have been productized in industry-leading EDA products that have been foundational to the semiconductor industry. Iyer earned a bachelor’s degree in electronics from the University of Bombay in India and a master’s degree and Ph.D. in electrical engineering from the Illinois Institute of Technology, which honored him with a Distinguished Alumni Professional Achievement Award in 2010. He currently serves on the external advisory board of the ECE department at the Illinois Institute of Technology. In 2017, Iyer completed the Executive Accelerator Program at Stanford University’s Graduate School of Business. Iyer has published approximately 40 papers on various EDA topics and has 90+ issued or pending patents in related fields. Iyer was named a Synopsys Fellow in 2006, an Altera Fellow in 2013, an Intel Fellow in 2016, and an Intel Sr. Fellow in 2021. Mahesh was elevated to IEEE Fellow for his leadership contributions to ASIC and FPGA Electronic Design Automation.