The manufacturing yield challenge of three-dimensional integrated circuit (3D ICs) is one of the key obstacles in the industry adoption of 3D integration based on through-silicon-vias (TSVs). The addition of spare TSVs to repair faulty functional TSVs is an effective method for yield and reliability enhancement, but this approach results in significant hardware cost and delay overhead. Most existing solutions are only suitable for a “dual-uniform” scenario in which both the placement and the defect probabilities of functional TSVs are assumed to be uniform. In this paper, we propose a design technique that is compatible with non-uniform TSV placement and it can repair faulty TSVs based on a realistic clustered defect-distribution model. The proposed solution is based on two consecutive stages, which utilize a greedy algorithm and an integer-linear-programming formulation, respectively. By considering the trade-off between chip yield, hardware cost, and delay overhead, the proposed technique provides higher yield and reliability under a clustered defect distribution, and with minimum hardware cost and delay overhead, compared to the previous work.