paper
Transition Fault Simulation
Publication
Volume Number:
4
Issue Number:
2
Pages:
Starting page
32
Ending page
38
Publication Date:
Publication Date
1 April 1987
paper Menu
Abstract
Delay fault testing is becoming more important as VLSI chips become more complex. Components that are fragments of functions, such as those in gate-array designs, need a general model of a delay fault and a feasible method of generating test patterns and simulating the fault. The authors present such a model, called a transition fault, which when used with parallel-pattern, single-fault propagation, is an efficient way to simulate delay faults. The authors describe results from 10 benchmark designs and discuss add-ons to a stuck fault simulator to enable transition fault simulation. Their experiments show that delay fault simulation can be done of random patterns in less than 10% more time than needed for a stuck fault simulation.
Country
USA
